A Nonuniform Sampling ADC Architecture With Reconfigurable Digital Anti-Aliasing Filter

This work proposes a nonuniform sampling analog-to-digital converter (ADC) architecture that incorporates a reconfigurable digital anti-aliasing (AA) filter in the asynchronous digital domain. Considering applications where the signal frequency, bandwidth, or activity may significantly vary over time and operating conditions, it provides high flexibility, relaxes analog AA filter requirements, adapts its sampling rate according to the incoming signal, and interfaces seamlessly with synchronous digital processers. In addition, the proposed ADC architecture relaxes voltage quantization by introducing time quantization, which favors future technology scaling. Furthermore, approximated analytical noise models are derived to study the underlying quantization effects on the proposed digital AA filter. It explores the theoretical bounds of achievable signal-to-noise ratio (SNR) given different ADC and filter design parameters. Finally, some hardware design considerations and limitations are discussed.