Multi-context non-volatile content addressable memory using magnetic tunnel junctions

As we are approaching the physical limits of the miniaturization of CMOS structures, the magnetic tunnel junction with spin transfer torque programing (STT-MTJ) are under intense investigation for power reduction for both memories and logic function implementations. In this paper, we present a novel design of non-volatile content addressable memory (NV-CAM) using STT-MTJs and logic-in-memory (LIM) architecture. In this NV-CAM, multiple memory cells share the same comparison circuit to provide area efficiency. A non-volatile switching circuit (NV-SC) has been developed for word line selection. If there is an occurrence of an unexpected power-off, search operation starts again from the stored word line instead of the beginning of the comparison sequence. Hence, the overall energy is further reduced. By using an industrial CMOS 28 nm design kit and a MTJ compact model, we validate the functionality of proposed NV-CAM and confirm its merits of high speed, low power consumption and low bit-cell cost.