Low ON-Resistance SiC Trench/Planar MOSFET With Reduced OFF-State Oxide Field and Low Gate Charges

We propose a SiC trench/planar MOSFET (TP-MOS) which features a trench channel and a planar channel in one half-cell. Numerical simulations with Sentaurus TCAD have been carried out to study the proposed device architecture. Compared with traditional planar MOSFET (P-MOS), the TP-MOS has a much lower
${R} _{\mathrm {ON}}$
owing to the increased channel density. Unlike traditional trench MOSFET (T-MOS) which enables a higher channel density at the price of a high bottom-oxide field in the high-voltage OFF-state, the TP-MOS features bottom p-bases as in the P-MOS that protect the gate oxide from high electric field. The OFF-state oxide field in the TP-MOS is found to be even lower than the P-MOS. In addition, the TP-MOS boasts a low feedback capacitance (
${C} _{\mathrm {rss}})$
and gate-to-drain charge (
${Q} _{\mathrm {GD}})$
, since the coupling between the gate and the drain is suppressed by the collective effects of the top p-bases and the bottom p-bases. The
${Q} _{\mathrm {G}}$
of the TP-MOS is nearly the same as the P-MOS, and is much smaller than the T-MOS. Superior figures of merit (
${Q} _{\mathrm {G}}\times {R} _{\mathrm {ON}}$
and
${Q} _{\mathrm {GD}}\times {R} _{\mathrm {ON}})$
are achieved in the TP-MOS.