Buffer-controlled cache for low-power multicore systems

This paper proposes a buffered dual-access mode cache to reduce power consumption in multicore embedded systems. This cache is called as Buffer-Controlled Cache (BCC). The proposed cache includes a pre-cache buffer to determine how to access the cache in two different ways. The BCC scheme shows better prediction rates and lower power consumption than other popular low-power caches, such as Phased cache and Way-prediction cache. We have used Multi2Sim and McPAT simulators to evaluate various cache systems by using the multicore-oriented Parsec benchmark programs. Our experimental results show that the proposed cache scheme improves the power consumption by 54% over the other popular cache scheme, such as Way-prediction cache.