Low-Power and Low-Noise Capacitive Sensing IC Using Opamp Sharing Technique

This letter presents a low-power and low-noise capacitive sensing IC using opamp sharing technique. The proposed IC reduces both the power consumption and the required circuit area using the opamp sharing technique while maintaining low noise characteristics. A correlated double sampling technique is adopted to reduce the low-frequency noise, including the 1/f noise. An automatic offset calibration loop can automatically reduce the offset parasitic capacitance in the range from -10.8 to +10.8 pF. The power consumption and the active circuit area are 1.02 mW and 2.12 mm
²
, respectively. The integrated input referred capacitance noise is 0.164 aFRMS with a bandwidth of 400 Hz.