High-level hardware-software co-design of an 802.11a transceiver system using Zynq SoC

Modern-day wireless communications standards are constantly evolving to meet the needs of an increasing number of devices. To adapt to these trends, software-defined radio has garnered more interest. In order to adapt to evolving standards while maintaining strict timing constraints, heterogeneous computing has been explored. In this demonstration, we take a new approach to the design of an 802.11a transceiver system on a heterogeneous system, the Zynq SoC. We take high-level Simulink models and develop several variants to enact different boundaries between components targeted for hardware and software. We then auto-generate C code from the software components and HDL code from the hardware components and use this to build both a CPU executable and an FPGA bitstream. We validate, profile, and analyze the models using metrics such as maximum step time per frame and FPGA resource utilization. Our results demonstrate how to select a co-design configuration for optimal operation of the 802.11a wireless standard.