RCA on FPGAs designed by the RTL design methodology and wave-pipelined operation

Field-programmable gate arrays (FPGAs) are used in various systems that use reconfigurable function. Conventional FPGAs have been developed by a transistor-level description for minimizing routing delay. Although FPGAs developed by the register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the authors have advanced their development. They should be shown to operate in a practical throughput. For this purpose, circuits on them need to be designed and evaluated. In this paper, a ripple-carry adder (RCA) is designed on them and the throughput of the RCA is evaluated. The throughput shows that it is applicable to network processors. In addition, a wave-pipelined operation without changing the RCA reveals that the problem of routing delay in the FPGAs developed by the RTL methodology is mitigated.