Timing Analysis and Optimization Based on Flexible Flip-Flop Timing Model

Presently, almost all timing analyses and optimization tools are based on the strategy of setup and hold time constrained flip-flop timing model. However, this is a big mismatch with the timing characteristic of the real life flip-flops, which is so called flexible flip-flop timing, in which the clock-to-Q delay of every flip-flop may vary dynamically according to its setup and hold skews. This work addresses the problem of timing analysis and optimization based on flexible flip-flop timing model, in which the key contributions are (1) proposing a flexible flip-flop timing model based clock-to-Q delay range analysis, (2) exactly formulating the clock period minimization problem as a representative application, and (3) proposing a scalable speedup technique which is able to drastically reduce the run time with no or very little loss of timing optimality. Through experiments with benchmark circuits, it is shown that our timing analysis and optimization technique are able to consistently shorten the clock period or improve the timing yield of design, compared to that produced by the prior techniques.