Modeling Residual Life of an IC Considering Multiple Aging Mechanisms

Counterfeiting and recycling of integrated circuits (ICs) is a significant threat to the safety and security of commercial and military systems. To deter recycled ICs from entering the supply chain, the residual life of ICs should be metered. Several aging sensors have been proposed to track the semiconductor degradation effects, but there are very few works to monitor multiple aging mechanisms and their cumulative effect on lifetime reliability. In this paper, we present an analytical model to directly measure the residual life of an IC based on its history of operating conditions. Unlike prior work, we compute residual life of an IC considering multiple aging mechanisms based on cumulative distribution function (CDF) of failure rate. The most important intrinsic silicon degradation mechanisms are time dependent dielectric breakdown, electromigration, hot carrier degradation, negative bias temperature instability and others. For the purpose of illustration, we narrow our focus on residual life modeling based on Time Dependent Dielectric Breakdown (TDDB), then generalize to account for multiple aging mechanisms. The model allows for physical implementation of residual life meter in an IC.