Foreword Special Issue on Advanced Technology for Ultra-Low Power Electronic Devices

Electronic devices consume a large amount of energy globally, and this is projected to accelerate in the near future with greater societal connectivity and cloud storage. To meet power saving goals, both the DC leakage power (
$\text{P}_{\mathrm{ DC}}$
) and switching AC power (
$\text{P}_{\mathrm{ AC}}$
) consumption of future electronics must be lowered. Electronic materials play a central role for ultra-low power electronics. To lower the transistor’s gate and source-drain leakage current, high-
$\kappa $
dielectric plus metal gate technologies and FinFET structures have been implemented in CMOS. The scaling of supply voltage (
$\text{V}_{\mathrm{ DD}}$
) is an effective way to lower
$\text{P}_{\mathrm{ AC}}$
, where the transistor’s current degradation can be compensated by using high mobility channel materials, such as p-channel Ge, and n-channel InGaAs; high-mobility metal-oxide semiconductors, or two-dimensional (2D) materials. The ultimate
$\text{V}_{\mathrm{ DD}}$
reduction is limited by the transistor’s turn-on slope. One proposed solution is the Tunnel FET, where carriers are injected by band-to-band-tunneling directly to the channel. Another method to reach <60 mV/dec turn-on slope is to integrate piezoelectric or ferroelectric materials into MOSFETs. These new electronic materials can also be used for ultra-low power memory application beyond existing DRAM thereby enabling technology for processor-in-memory and brain mimicking chips.