Extremely high simulated ballistic currents in triple-heterojunction tunnel transistors

Future VLSI devices will require low CV
_dd
²
/2 switching energy, large on-currents (I
_on
), and small off-currents (I
_off
). Low switching energy requires a low supply voltage V
_dd
, yet reducing V
_dd
typically increases /off and reduces the I
_on
/I
_off
ratio. Though tunnel FETs (TFETs) have steep subthreshold swings and can operate at a low V
_dd
, yet their I
_on
is limited by low tunneling probability. Even with a GaSb/InAs heterojunction (HJ), given a 2nm-thick-channel (001)-confined TFET, [100] transport, and assuming V
_dd
=0.3V and I
_oFF
=10
^-3
A/m, the peak tunneling probability is <;3 % (fig. 1 a) and I
_on
is only 24 A/m (fig. 1b) [1]. This low I
_on
will result in large CV
_dd
/I delay and slow logic operation. Techniques to increase /on include graded AlSb/AlGaSb source HJs [2,3] and tunneling resonant states [4]. We had previously shown that tunneling probability is increased using (11 0) confinement and channel heterojunctions [1], the latter increasing the junction built-in potential and junction field, hence reducing the tunneling distance. Here we propose a triple heterojunction TFET combining these techniques. The triple-HJ design further thins the tunnel barrier to 1.2 nm, and creates two closely aligned resonant states 57meV apart. The tunneling probability is very high, >50% over a 120meV range, and the ballistic I
_on
is extremely high, 800A/m at 30nm Lg and 475 A/m at 15nm Lg, both with I
_off
=10
^-3
A/m and V
_dd
=0.3 V. Compared to a (001) GaSb/InAs TFET, the triple-HJ design increases the ballistic /on by 26:1 at 30nm L
_g
and 19:1 at 15nm L
_g
. The designs may, however, suffer from increased phonon-assisted tunneling.