Density scaling beyond the FinFET: Architecture considerations for gate-all-around CMOS

The promise of improved electrostatics and the ability to increase the amount of effective width (Weff) available in a given device footprint drove the semiconductor industry from planar CMOS transistors to the FinFET transistor starting at the 22 nm node [1]. Numerous manufacturers are in large-scale production of 16 and 14 nm node FinFET technologies [2-3] and there is no indication that a change in device architecture is planned for the 10 or 7 nm nodes [4]. Looking beyond 7 nm, the scaling challenges of the FinFET are expected to increase dramatically. In particular, continued scaling of the fin width and fin pitch may reach a physical limit due to a combination of quantum effects, patterning process [5] realities and contact architecture limitations [6]. It is well known that gate-all-around (GAA) devices demonstrate improved electrostatics over double or triple-gated FinFET devices [7]. In view of the impending difficulties occasioned by FinFET scaling, it is necessary to take a critical look at the possibility of a GAA CMOS device technology. In this paper, I will explore this topic by presenting relevant TCAD and experimental work on single and stacked GAA devices. The TCAD illustrates that a properly designed stacked GAA device architecture can show superior performance over a scaled FinFET reference. I will conclude by presenting experimental work to substantiate this claim.