Analysis and Reduction of Nonidealities in Stacked-Transistor Current Sources

An in-depth analysis of nonidealities of CMOS stacked-transistor current sources is presented. This analysis quantifies the impact of series parasitic resistance on the systematic error of stacked-transistor current sources and the effect of partition ratio/partition number on the random mismatch of stacked-transistor current sources. The analytical results are presented in closed-form formulas that enable the explanation of many second-order effects seen from circuit simulation. Various tradeoffs in the design of stacked-transistor current sources are discussed. A weighted sizing technique based on the analytical results is proposed that can optimize the random mismatch of stacked-transistor current sources for a given area budget.