Tackling Roadblocks to Achieve Optimum DDR Performance

As the processor speed is increasing day by day with the advancement in technology, memory vendors are forced to come-up with newer solutions which could match the processor speed without impacting the overall system efficiency. That's why industry has moved from SDRAM era to DDR4 era where memory is running at a speed more than 3GHz. DDR memory devices have been optimized for maximum speed and minimum power possible by the manufacturers, but are these enough to get the best out of any SOC? There are several parameters present at memory controller and SOC level which could impact the performance in a greater way and if they are not taken care appropriately, it could result into an inefficient system. Without optimizing those parameters, it is impossible to get the best outcome from the memory it is designed for. This paper throws light on those parameters and shows some result that how significantly DDR performance improves by optimizing those parameters. This paper also talks about system level scenarios where graphic controller is accessing DDR3 memory and how its read/write performance was increased within given cycles. It also describes different profilers used in hardware to measure the performance in an efficient manner.