A Fast Multi-valued Sbnr Multiplier

A novel multi-valued SBNR Multiplier architecture using redundant numbers in the encoded partial product generators is described. The architecture employs an efficient blend of voltage- mode and current-mode cells in an attempt to overcome the deficiencies of each mode employed separately. Our methodology capitalizes on the salient properties of multi-valued and binary techniques within a systems context. A brief review of VLSI techniques for multi-valued lo IC implementations is provided, including CDIOS, I L, ECL, TSL, and STL. Advantages and disadvantages of each technology are given as well, with a focus on multi-valued logic (MVL) applications.