Study of Chip Stacking Process and Electrical Characteristic Evaluation of Cu Pillar Joint Between Chips Including TSV

Three-dimensional chip stacking is a useful integration technology for improving electrical performance. In this study, we manufactured two different-sized stacked chips and examined the stacking process and electrical properties of a Cu pillar joint with a through-silicon via (TSV). To achieve alignment accuracy, a stacking process using reflow with reduction atmosphere was evaluated. As a result, the reflow process ensured bonding accuracy and the successful joining of a CuSn intermetallic compound. To determine electrical characteristics, we evaluated the electro-migration of the Cu pillar intermetallic compound (IMC) joint, which resulted in problems with small inter-chip connection. It was clarified that there was no damage to the TSV or TSV joint from the current flow, and the lifetime of the Cu pillar joint constructed with a CuSn IMC was determined to have improved by several times compared with a conventional Cu pillar and a solder joint.