Low Cost Wafer Level Packaging of MEMS Devices by Vertical Via-Last Process

MEMS devices are continuous evolving to achieve smaller size and lower cost with improved performance. The Through silicon via (TSV) technology offers a promising approach from the perspective of MEMS device packaging and integration. In this paper, we report our latest progress on wafer level packaging of MEMS devices by via-last process. The 200mm MEMS wafer was bonded with a glass cap wafer. Then, the vertical TSV structure with aspect ratio of 3:1 was realized from the device wafer side. The silicon vias are insulated by PECVD silicon dioxide. All the process steps are realized at the wafer level using the state-of-the-art facilities. The via-last integration, electrical test and reliability test are performed. The open/short electrical test results approve the principle, and the reliability test results further convince the developed via last process. This paper introduces a robust and cost-effective solution for heterogeneous 3D integration.