Ultra Fine Pitch / Low Cost FCCSP Package and Chip Package Interaction (CPI) for Advanced CMOS Nodes

The advancement of Si and flip chip package technologies are driven by high performance mobile processors with high I/O counts. In Si, the back-end-of-line (BEOL) copper interconnect with extreme low-K (ELK) dielectrics has been used to lower RC latency. While for packages, fine-pitch Cu bump is introduced to meet the high I/O density. Corresponding assembly solutions such as thermal compression bonding (TCB) has been used to meet fine-pitch die bonding accuracy requirement. However, the process cost is high due to tool investment and low throughput. Mass reflow, in contrast, supporting processes in batches, enables low cost fine pitch solution. This paper presents the Chip-Package-Interaction (CPI) and assembly process characterization based on the advanced Si incorporated with (1) 60 um pitch Cu bump-on-trace (CuBOT), (2) thermal reflow, and (3) BOT substrate with one escaped trace between bumps. CPI and assembly challenges including ELK peeling, bump bridging, and Cu trace peeling will be investigated. Effects of bump structure, UBM design, polyimide (PI) opening, and substrates material on ELK stress and assembly yield will be addressed. In addition, wafer probing effects on CuBOT packaging yield and reliability will be discussed. Quick temperature cycle (QTC) test for ELK robustness check is employed to speed up Si and bump structure optimization. Full ELK stacking samples with encapsulation passed reliability qualification under JEDEC test conditions. Bias-HAST is further conducted to confirm the process integrity for fine-pitch substrates. Current carrying capability of fine pitch Cu bump is identified by electron-migration (EM) test as well.