Electrical Model of Different Architectures of through Silicon Capacitors for High Frequency Power Distribution Network (PDN) Decoupling Operations

The "Through Silicon Vias" technology, developed for silicon interposer interconnects network, has inspired new capacitor components named "Through Silicon Capacitors (TSC)". Two architectures of TSC are studied in this paper: the Single Sided-TSC (SS-TSC) and the Double Sided-TSC (DS-TSC). Both of them use the third dimension of the silicon interposer to integrate cylindrical MIM capacitors. The SS-TSC bodies are connected in parallel by the BEOL metal layers M1 and M2. The Double Sided-TSC bodies are connected in parallel by using Metal 1 layer and the RDL layer located respectively on the front side and the back side of the silicon interposer. Modeling methods based on a segmented approach are presented for each architecture. Measurements on a large frequency range [100 Hz - 40 GHz] by using an Impedance Analyzer and a Vectorial Network Analyzer are performed on prototypes of the SS-TSC architecture and the results allow to validate the corresponding modeling method. Next, a comparative study of those two architectures is performed. The electrical performances of those two architectures components are compared for different sizes of matrices and defined integration scenarios based on access impedance reduction and frequency limitation according to the current propagation through the TSC.