A Comparison of Error Performance for Iterative Calculation in MSA Decoder for LDPC Nonregular Parity Check Matrix in 16QAM System

Based on the lower density parity check matrices in approximate lower triangular form allowed by the IEEE P802.11n/D1.04 (Part 11: Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) Specifications) standards, LabVIEW FPGA programming language was used in this study to construct an encoder with a contract advantageous in the implementation of the hardware circuit that can generate codewords in various conditions, including four code rates (1/2, 2/3, 3/4, 5/6) and three subblock sizes (27, 54, and 81 bits), and a decoder that used the minimum sum algorithm. The program can encode and decode signals by first selecting code rate and subblock size and then changing the structure of the check and variable nodes accordingly. In this study, a detailed introduction to minimum-sum algorithm and the decoding mechanism was provided, the decoding program was optimized, and decoding performance was analyzed using bit error rate (BER) efficiency curves. In addition, the decoder was simulated under an additive white Gaussian noise channel with a noise ratio Eb/N0 ranging from 0 dB to 10 dB. Decoding performance for various combinations of code rate and subblock size were compared by generating BER efficiency curves for these combinations. Simulation results showed that subblock size did not affect BER, but code rate did. BER resulting from 16 quadrature amplitude modulation was compared to BER from quadrature phase-shift keying, binary phase-shift keying, and the 802.11n and 802.16e standards.