A SPICE Model of the $\textrm{Ta}_{2}\textrm{O}_{5}/\textrm{TaO}_\textrm{x}$ Bi-Layered RRAM

Designing a SPICE model is a critical step toward understanding the behavior of the resistive random access memory (RRAM) devices when integrated in memory design for the future generation storage devices. In this paper, a SPICE model is developed for the Ta
₂
O
₅
/TaO
_x
bi-layered RRAM. The proposed model emphasizes the impact of the change in the switching layer thickness on the device behavior at low resistance state (LRS), high resistance state (HRS), and the transitional period. The validity of the proposed model is verified through using three different sets of experimental data from Pt/Ta
₂
O
₅
/TaO
_x
/Pt RRAM with switching layer thickness smaller than 5 nm. The SPICE model reproduced all the major features from the experimental results for the SET and RESET processes and also the asymmetric and the symmetric characteristics in HRS and LRS, respectively. The proposed SPICE model matches the measured experimental results with an average error of <; 11% and a maximum error of <; 70%. It also showed stable behavior for its HRS and LRS regions under different types of input signals. The model is parameterized in order to fit into Ta
₂
O
₅
/TaO
_x
RRAM devices with switching layer thickness smaller than 5 nm, thus, facilitating the model usage. The model can be included in the SPICE-compatible circuit simulation and is suitable for the exploration of the Ta
₂
O
₅
/TaO
_x
bi-layered RRAM device performance at circuit level.