ESD reliability evaluations of the 60-V nLDMOS by the drain-side discrete SCRs

The influences of ESD protection capability and latchup immunity in 60-V high-voltage N-channel LDMOS transistors by the drain-side discrete and embedded SCR structures are investigated in this paper. From the transmission-line pulse (TLP) testing results, the trigger voltage (V
_tl
) and holding voltage (V
_h
) of these DUTs with a drain-side parasitic SCR have a upward trend when the width (S) of STI increased. Meanwhile, the secondary breakdown current (I
_t2
) correlated to the anti-ESD capability of the drain-side "npn" arranged-type has a downward trend with the STI parameter S increased. But, the I
_t2
values of the "pnp" arranged-type are larger than 7 A, and its robustness of the "pnp" arranged-type are greater than the "npn" arranged-type.