Design of a 10-Gbps random number recorder

We design a Data Acquisition (DAQ) system for a 10-Gbps true random number generator to verify the quality of the random number. The prototype of the DAQ is based on a Xilinx Vertex-6 FPGA evaluation board. The DAQ system has three parts: acquisition, cache, and data up-link. Acquisition is the interface to the high-speed random data, and we use Gigabit Transceiver (GTX) in FPGA to deserialize the random data. The 1Gbps high speed serial random data in each channel is deserialized into 62.5Mbps with 16bit width parallel data. The low speed parallel data can be handled by the FPGA code and cache the data in an external DDR3 memory. When enough random data is stored, the random data is upload to PC via Gigabit Ethernet for the finial verification. The BERT test shows that the total data error rate of the data link in the prototype is less than 6.25×10
^-1
° with 1Gbps input. The prototype can cache up to 16Gbits random data with 1Gbps serial input, and it meets the requirements of the data acquisition for one channel of the random number generator and proves the DAQ structure.