Offset word line architecture for scaling DRAMs to the Gigabit level

Scaling technology for future DRAM generations has become increasingly more difficult. A key limitation is the non-scaling of threshold voltage V
t
. Various techniques have been investigated to overcome this problem: boosted word line[1], boosted storage node[2] and on chip voltage level generation to provide a reduced bit line voltage swing [3]. However, these techniques impact performance or reliability. The problem makes DRAM design below 2.5 volt supplies unlikely, and would prevent the scaling of DRAMs beyond 64 Megabits[4], A new array architecture which provides a larger voltage swing for the word line without increasing the gate dielectric field in the word line driver or array access device is described below. The increased voltage can be greater than the required threshold voltage even for Gigabit Scale Integration (GSI) level DRAM technologies. The new array architecture is called an Offset Word Line architecture.