A 46ns 1Mbit CMOS SRAM

This paper reports on a 1Mbit (128Kword × 8bit) SRAM using an advanced CMOS process technology. The typical address access time of 44ns and chip-select access time of 46ns are achieved with the power dissipation of 80mW for 1MHz operation. This SRAM employs a column DC bit-line load control to reduce power dissipation in the write mode operation. It also has an additional testing mode to access 4byte at one time to reduce the testing period.