Investigation of TSV noise coupling in 3D-ICs using an experimental validated 3D TSV circuit model including Si substrate effects and TSV capacitance inversion behavior after wafer thinning

This paper investigates the influence of TSV noise coupling on nearby devices based on an extended 3D TSV circuit model. This model not only takes into account the complex RF field distributions in bulk Si, but also incorporates the anomalous TSV capacitance inversion behavior, which has been found to occur due to the presence of fixed charges in the backside passivation layer after wafer thinning. The extended 3D TSV circuit model is validated by the excellent agreement between the simulation results and experimental data. It demonstrates that the inversion behavior of the TSV capacitance increases the noise coupling to adjacent devices mainly in the low frequency range. Furthermore, we show that noise mitigation techniques can be easily implemented in this 3D circuit model to predict the extent of noise coupling alleviation.