A 2.8–6 GHz high-efficiency CMOS power amplifier with high-order harmonic matching network

An output matching network with high-order harmonic matching is proposed for wideband power amplifier (PA) design, which obtains wideband fundamental load-pull matching and first two order harmonic matching for efficiency improvement simultaneously. The proposed power amplifier is implemented in 0.18-µm CMOS process. Within the 3-dB small signal bandwidth from 2.8 to 6 GHz, it achieves more than 20.8–dBm Psat and 20.3–dBm OP1dB. In the meanwhile, the peak power added efficiency (PAE) is from 37 to 44%, and PAE at P1dB is from 33 to 38%. The circuit shows the best efficiency performance compared with the published broadband CMOS PAs in similar frequency band.