A broadband compact low-loss 4×4 Butler Matrix in CMOS with stacked transformer based quadrature couplers

This paper presents an ultra-broadband ultracompact Butler Matrix design scheme. The design employs stacked transformer based couplers and lumped LC π-network phase shifters for substantial size reduction. As a proof-of-concept design, a 4×4 Butler Matrix is implemented in a standard 130nm bulk CMOS process at a center frequency of 2.0 GHz. Compared with reported fully integrated 2.0 GHz 4×4 Butler Matrix designs in CMOS, the proposed design achieves the lowest insertion loss of 1.10dB, the smallest amplitude mismatch of 0.3 dB, the largest fractional bandwidth of 34.6%, and the smallest chip core area of 0.635×1.122 mm2. Based on the measured S-parameters, the four concurrent electrical array patterns of the Butler Matrix achieve array peak-to-null ratio (PNR) of 29.5 dB at 2.0 GHz and better than 15.0 dB between 1.55 GHz and 2.50 GHz.