Small signal modelling approach for submillimeter wave III–V HEMTs with analysation and optimization possibilities

In this paper we present a new small signal multiport modelling approach for III-V High Electron Mobility Transistors (HEMT) that is capable for internal transistor analysation and optimization as well as scaleable in gate width and finger-number. The new model decomposes the planar transistor structure into single multiport elements that are separately described by electrical equivalent circuits and connected to each other over discrete ports. With this new modelling topology we only need to extract a couple of multiport elements to predict the correct behavior for a high amount of different planar transistor structures. This point gives the circuit designer a wide range of possibilities to analyze and optimize a given transistor structure according to special needs, like low-noise, input-output matching or cryogenic behavior on a computer based level.