Simulation Study of Single-Event Burnout in Power Trench ACCUFETs

This paper presents 2-D numerical simulation results of single-event burnout (SEB) in power trench accumulation mode field effect transistor (ACCUFET) for the first time. In this device, a p
⁺
base region is used to deplete the n
^-
base region to achieve a low leakage current density, and the blocking voltage is supported by the n
^-
drift region. We find that the depth of the p
⁺
base region determines both the leakage current density and SEB performance, as a result, there is a tradeoff relationship between the two characteristics. The 60 V hardened power ACCUFET shown in this paper could demonstrate much better SEB performance without sacrificing the current handling capability compared with the standard UMOSFET. The hardened structure mentioned in this paper indicates that an n buffer layer is added between the epitaxial layer and substrate layer based on a basic power device. As a result, the safe operating area (SOA) of the 60 V, 80 V and 100 V hardened ACCUFET discussed in this paper could reach the value of breakdown voltage when the buffer layer is over a certain value, that can realize safety operation throughout entire LET range.