FPGA-Based Hardware Implementation of Real-Time Optical Flow Calculation

Optical flow calculation algorithms are hard to implement on the hardware level in real-time, due to their complexity and high computational load. Therefore, presented works in the literature focusing on the hardware implementation are limited. In this paper, we present a hierarchical block matching-based optical flow algorithm suitable for real-time hardware implementation. The algorithm estimates the initial optical flow with block matching and refines the vectors with local smoothness constraints in each level. We evaluate the proposed algorithm with novel data sets and provide results compared with the ground truth optical flow. Furthermore, we present a reconfigurable hardware architecture of the proposed algorithm for calculating the optical flow in real-time. The presented system can process $640\times 480$ resolution frames at 39 frames/s.