STT-MRAM write energy minimization via area optimization under dynamic voltage Scaling

In this paper we show that the area optimization of STT-MRAM bitcells can deliver a substantial reduction in the energy per write access when dynamic voltage scaling (DVS) is adopted. Indeed, the increase in the bitcell area enables the reduction in the write energy consumed by the bitcells at the expense of the energy of peripheral circuits, when lowering the supply voltage. The proposed approach addresses a fundamental challenge in STT-MRAM arrays, whose energy efficiency is well-known to be severely degraded by the large energy cost of write. Simulations of STT-MRAM arrays built with four widely adopted bitcells showed that up to 2.5X write energy reduction and 5X performance improvement are obtained at 2X bitcell area cost at 0.7 V, compared to minimum-sized bitcell.