PVT-aware digital techniques for a power line energy-harvesting sensor node

Digital circuits are more resilient to PVT variations, has smaller area and lower power consumption than analog circuits. In this paper, two digital techniques, wait state and time slot, were used to solve the timing failures in the operation of the digital processing block of a power line sensor node. In this sensor node design, timing failures occur because of two reasons: 1) the power-on reset (POR) circuits are switching early and 2) the storage capacitor of the energy harvesting block cannot fully support the required energy during transmit operations. Using wait states, timing failures were prevented by providing timing margin between the POR switching and the activation of the digital blocks. The counters to implement the wait states only contributed 2% additional area and 5% addition al power consumption to the digital processor. The time slot technique, on the other hand, prevented timing failures by providing a schedule for the transmit operation to execute only at a time when Pin is higher than P
_transmit
. Using this technique, the size of the storage capacitor of the energy harvesting block was reduced 50 times compared when the technique is not used. The power line sensor node was successfully fabricated in 65nm CMOS process with an area of 4.84mm
²
and was designed to work at a noisy voltage supply of 500mV with a voltage ripple of 15mV peak to peak and a wide temperature range of 0°C to 120°C.