A novel computationally-efficient digital frequency locking scheme for software defined radio MODEM

In this paper a novel simple all digital frequency locking circuit design is presented together with its performance results. The proposed method can be used to lock DDSs to a reference clock such as a data clock. It allows for efficient fully multi-rate modem design (with a resolution bound by the DDS) within a low cost FPGA. In fact, using the new scheme the baseband modem can be completely constructed within the FPGA without external complicated and expensive VCOs and their associated locking loops.