In-package harmonic termination design for improving active device efficiency

This paper discusses design of in-package reactances that can optimize efficiency of power amplifier transistors by specific and well-defined harmonic terminations and pre-matching within the device package. The methodology uses a passive fundamental-only load-pull tuner to characterize the transistor. As an example, the method is applied to a 10-W Infineon LDMOS device at a fundamental frequency of 2.6 GHz, by terminating the 5.2-GHz second harmonic using bond-wire and capacitor filters of various topologies. A 60% PAE is achieved with the method.