3-D simulation study of high performance, area efficient integrated FET

FinFETs are the most promising candidates for the future scaling technology beyond the scaling limits of conventional CMOS technology. The scaling of the conventional planar MOSFET has been facing problems such as subthreshold swing, significant DIBL, fluctuations of device characteristics and leakage. These problems can be solved using multi-gate devices. In this work, integration of 3-D non-planar fins and 2-D ultra-thin bodies on SOI platform is done to improve the transistor performance of a 18nm gate length device and its performance is compared with conventional tri-gate FinFET. The short channel effects such as Drain Induced Barrier Lowering is reduced to 74% with the use of an Ultra-Thin Body above Buried Oxide and subthreshold swing up to 76.5%. The device is also suitable for high power applications with Ion/Ioff ratio of the device being 10
⁷
.