Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning

Frequent item set mining algorithms have proved their effectiveness to extract all the frequent itemsets in datasets, however in some cases they do not produce the expected results in an acceptable time according to the application requirements. For this reason, FPGA-based hardware architectures for frequent item set mining have been proposed in the literature to accelerate this task. Most of the reported architectures are limited by the number of distinct items that could be processed and the available resources in the employed FPGA device. This study proposes a compact hardware architecture for frequent item set mining capable of minimg all the frequent itemsets regardless of the number of distinct items and transactions in the dataset. The proposed architectural design implements a partition strategy based on equivalence classes. The partition on equivalence classes allows to divide the search space into disjoint sets that can be processed in parallel. Accordingly, a parallel architecture is proposed to exploit the benefits of the proposed search strategy.