A Rapid Prototyping Method to Reduce the Design Time in Commercial High-Level Synthesis Tools

High-Level Synthesis (HLS) tools have been developed to increase the abstraction level of hardware design process, by using models like high-level programming languages (e.g. C/C++), Domain Specific Languages and Graphs. However, despite their advances in the last decade, the available HLS tools still require from the designer a broad hardware knowledge, which prevents a bigger reduction in the design time. In this work, we propose a method to be used at the top of current high-level synthesis tools, allowing for a speed-up in the development process. The method starts with the application description in a subset of the ANSI-C language. Then we generate a Graph from the C source code. There is a finite number of possible nodes, and this fact allows the creation of a database of alternative hardware models for each possible node type. A simple optimization algorithm selects the combination of nodes which best fits under the constraints (power consumption, resource use, speed). If a node is not in the database or the constraints were not met, then the designer can use any commercial high-level synthesis tool (or a direct RTL description), to create a new hardware model and include it in the database. Some test cases were implemented using both the proposed methodology and a commercial HLS tool. The results obtained indicate that the method can reduce the design time while still providing fair results when compared to the commercial tool.