Low-cost dithering generator for accurate ADC linearity test

The ultrafast segmented model identification of linearity error (uSMILE) algorithm dramatically reduces ADC linearity test time while achieving superior test accuracy. This method avoids the gross inefficiencies in the conventional histogram test method to reduce the test data by a factor of over 100. However, in low noise environment where the quantization noise becomes dominant, uSMILE leads to large (up to +/-0.5 LSB) INL estimation error. In this case, proper extra noise needs to be added to the stimulus in order to whiten the quantization noise. In this paper, a pseudo random dithering method and a low-cost implementation of dithering generator in SAR ADC are proposed. The random pattern is generated from a simple shift register and XOR gate. The dithering is added through the dummy capacitor of SAR ADC during the ADC sampling phase. The proposed scheme is validated through extensive simulations. The maximum INL estimation error in a 12-bit ADC with 1 hit/code ramp test is within ± 0.1LSB.