Area-optimal sensing circuit designs in deep submicrometer STT-RAM

As the technology node scales down, a sufficient read current that is capable of achieving a target read yield cannot be used because of the read disturbance problem in spin-transfer-torque random access memory (STT-RAM). As an alternative method, increasing the sensing circuit (SC) area is generally considered because it can reduce the threshold voltage (Vth) variations. However, the increased SC area can adversely reduce the read yield due to the increased load capacitance. The effects of the increased area on read yield can be different according to the SCs because of their own characteristics. In this work, the trends of read yield according to the area are analyzed for two representative SCs, and the areas of two SCs are optimally designed to have high read yield.