A hybrid comparator for high resolution SAR ADC

Together with the increasingly demanding DAC, the design of the comparator introduces a big challenge for the implementation of high resolution SAR ADCs. Therefore, several state of the art works investigated improved comparator architectures aiming for higher resolution. However, those architectures in most cases resulted either in excessive power consumption or compromised conversion speed. For improved performance and power efficiency this paper proposes the use of two dynamic comparators in a 14-bit SAR ADC. The first coarse decisions are made by a low power comparator, while the second comparator applies an automatic noise reduction technique to perform accurate decisions around the LSB. The proposal includes SAR conversion which applies two switching schemes a monotonic and a differential one. The design is partially implemented and simulated on transistor level using a 40 nm CMOS technology. The ADC is operated with a sampling frequency of 1.6 MS/s and features an SNDR above 81 dB and an SFDR above 97 dB. The estimated power consumption of the two comparators is 44 μW and about 27 μW for the DAC reference.