A 0.4V 1.94fJ/conversion-step 10b 750kS/s SAR ADC with input-range-adaptive switching

This paper presents a low-voltage and power-efficient 10-bit successive-approximation register (SAR) analog-to-digital converter (ADC). An input-range-adaptive (IRA) switching method is proposed to reduce the average switching power of capacitive-DAC (CDAC). By utilizing the comparator as a voltage-to-time converter (VTC) and implementation of time-domain quantizer, the input range is detected to efficiently eliminate the unnecessary CDAC switching power. A prototype ADC chip is fabricated in 90nm CMOS technology with an area of 0.038mm
²
, a Nyquist-rate input of 750kS/s, and a power consumption of 780nW at 0.4V supply. It achieves 9.0-ENOB and a resulting FoM of 1.94fJ/conversion-step.