Area-efficient partial-clique-energy MRF pair design with ultra-low supply voltage

As the size of CMOS devices continues to scale down, the reliability of circuits becomes one of main challenges in low supply voltage designs. Markov Random Field (MRF) circuits, a probabilistic-based approach, can achieve higher noise immunity compared to traditional designs under conditions of ultra-low supply voltage and low threshold voltage. However, the basic MRF elements have complex structures and become a stringent factor that limits MRF-based VLSI design. In this paper, we provide a partial-clique-energy MRF (PMRF) design method, trading off the noise immunity for area efficiency. We then propose an Enhanced PMRF (EPMRF)-pair for multi-level and multi-function joint PMRF designs. The main idea is to use the joint clique energy of two complementary partial clique energies to make up performance losses. The measurement results show that, the proposed EPMRF pair can operate at 0.25 V with 10-4 dB output noise power with 5.6 dB input signal-noise ratio (SNR). With the 130 nm CMOS technology, the chip of our EPMRF based carry-look-ahead adder achieves 29% area-saving and 55% energy-saving compared to existing ultra-low supply voltage fault tolerant designs.