A 1V, 1.1mW mixed-signal hearing aid SoC in 0.13μm CMOS process

In this paper a full chip implementation of a Mixed-signal hearing aid SoC is presented. The chip integrates Analog Front-End (AFE), Time-Division Multiplexed Power-On-Reset circuit (TDM-POR), Charge Pump (CP), Digital Signal Processing (DSP) platform and Class-D amplifier. Also, the Low-Dropout (LDO) voltage regulators and On-chip oscillator are both integrated to minimize the system overall size. The proposed SoC has been fabricated in SMIC 0.13μm CMOS process. The measurement results show that the peak Signal-to-Noise Ratio (SNR) of AFE is 82dB and peak SNR of Class-D amplifier is 79.6dB. And the DSP platform executes three hearing-aid algorithms of wide dynamic range compression (WDRC), noise reduction (NR), and feedback cancellation (FDC). The total SoC consumes 1.1mA from single 1V supply and occupies 9.3mm2. Finally a prototype of hearing aid device is designed and passes the industrial acoustic test which shows the chip is promising for mass production in future.