A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC

This paper presents a time-to-digital converter (TDC) using delta-sigma (ΔΣ) architecture which utilizes a charge pump as the time to voltage converter and a low bit SAR ADC as the quantizer. By never resetting the capacitor connected to the charge pump, a simple integrator is realized and first order noise shaping is achieved. This TDC is designed and simulated in 65 nm CMOS technology and can operate at 200 MHz sampling frequency. For 1 MHz bandwidth, simulation shows that this TDC achieves 74.9 dB SNDR and 269 fsrms integrated noise for ±1.5 ns input range. The proposed TDC consumes 0.9 mW power from 1 V power supply that translates to FoM of 99 fJ/conv.