FinFET cells with different transistor sizing techniques against PVT variations

This paper investigates the impact of the main sources of variation on performance and power consumption for different transistor sizing techniques applied to cells in FinFET technologies. The analysis considers process, voltage and temperature variations, individually. Voltage and temperature variations are combined to obtain an insight into their contributions. Results are useful to define the variability contributions in the early design steps and to select the most appropriate transistor sizing technique for a targeted application. Results provide a quantitative understanding of each contribution considering a 14nm FinFET technology.