Synchronised Microcontroller Architecture to eliminate dominant harmonics from Quasi square waveform

This paper explains a novel synchronised digital architecture for dominant (5th and 7th) harmonic elimination from a Quasi square waveform. The output waveforms of Inverters (DC to AC power converters) are in the form of square or Quasi square wave. There exists all odd harmonics in a Quasi square wave. The methods of harmonic elimination from the inverter output are variant in topologies and control methodologies. The multilevel (ML) inverter topologies provide quasi square wave or stepped output with abundant source of odd harmonics. To eliminate the harmonics from the ML inverter output, a microcontroller architecture is presented in this paper. A synchronised multicore architecture is used to synchronise between the control signals of an active compensator and the main ML inverter. To achieve a cost effective scalable solution a 8 bit low cost microcontroller and a single driver is used for each phase. The proposed design is implemented with a 8-bit PIC microcontroller (PIC18F452 and PIC18F4550) and applied on an IGBT (Insulated Gate Bipolar Transistor) based 2 KVA VSI with DC bus voltage of 100 V. Single cycle real time active harmonic compensation for dominant harmonic frequency (fifth and seventh) is demonstrated for 3-level voltage source inverter (VSI) with the experimental results..