Timing measurement BOST architecture with full digital circuit and self-calibration using characteristics variation positively for fine time resolution

This paper presents a time-to-digital converter (TDC) architecture to measure the timing difference between single-event two pulses with fine time resolution. Its features are as follows: (i) The architecture is based on stochastic process and statistics theory. (ii) It exploiting the stochastic variation in CMOS process for fine time resolution so that MOSFETs with minimum sizes are utilized. (iii) It needs a large number of D Flip-Flops (DFFs) for statistics but advanced fine CMOS technology can realize it. The larger the number of DFFs is, the finer the time resolution is. (iv) The self-calibration technique using the histogram method is applied to compensate the nonlinearity due to the circuit characteristics variation as well as timing skew by layout and routing. (v) The proposed TDC can be implemented with full digital circuit including the self-calibration circuit. Register-Transfer-Level (RTL) simulation has been conducted to validate the operation principle. RTL verification results indicate that the proposed stochastic architecture with self-calibration feature can realize a linear TDC with subpicosecond time resolution. The proposed TDC can be used for IC testing, high-speed data transfer testing and clock jitter measurement as well as physical experiments and laser ranging.