Area optimization methodology for RFIDs combining capacitors placement within digital circuitry

Minimize integrated circuit area by crunching more and more digital logic in an ever diminishing area is a current trend in semiconductor industry. Frequently, higher transistor densities in digital circuits are achieved by the use all metal layers available for routing signals. However, when designing mixed signal circuits, such as RFIDs, capacitors and other passive components represent a significant area in the integrated circuit. This paper presents a method and apparatus to rethink the common view, that adding more logic in smaller areas always reduces the circuit area, by using a counter-intuitive approach. This method consists of exploring different capacitor types and their placement possibilities to reach an implementation with reduced area, along with a noise analysis flow to certify IC proper operation. Our solution empowers integrated capacitors to overlap digital circuits, reducing total circuit area, in spite of enlarging digital circuit area together with capacitor distribution approaches. A test-chip has been manufactured and tested to demonstrate the approach feasibility and preliminary results are presented. Moreover, area reduction for a commercial lowfrequency RFID has been estimated in over 17%, by overlapping a resonance capacitor and a digital circuit using the method and apparatus presented.