Dynamic behavior model for SEED analysis; extraction using surface response modelling

System Efficient ESD Design (SEED) requires dynamic behavior models from the devices and circuitry used along the protection chain, typically from the discharge point of entry at the PCB boundary i.e. connector up to the circuits on-chip to be protected. In-between this path there may be external ESD protection i.e. voltage clamping together with parasitic layout effects, interconnect path delay with specific transmission line properties, package design up to on-chip protection design with parasitic layout effects and ultimately the on-chip circuit(s) to be protected, being unpowered or powered.